Design of 2.4 GHZ CMOS Frontend for Bluetooth

Krug, Florian

Design of 2.4 GHZ CMOS Frontend for Bluetooth

Zusammenfassung

Inhaltsangabe:Abstract:
The Bluetooth wireless technology is the worlds new short-range RF transmission standard for small form factor, low-cost, short-range radio links between portable or desktop devices. The technology promises to eliminate the confusion of cables, connectors and protocols confounding communications between today high tech products.
In the first step a 2.45 GHz Low Noise Amplifier (LNA), intended for use in a Bluetooth receiver, has been designed in a standard 0.18 um CMOS process. The amplifier provides a simulated switchable forward voltage gain of +16 / -7.7 dB with a simulated noise Figure (NF) of only 3 dB while drawing 2.8 mA from a 1.8 V supply. The die area of the LNA (pads included) is 0.79 mm2.
In the second step a 2.45 GHz Power Amplifier (PA), also intended for the Bluetooth standard, has been designed in the same 0.18 um CMOS process as for the LNA. The class-A PA achieves a simulated forward gain (S21) of 23 dB and a simulated output 1 dB compression point (P1dB ) of 5.5 dBm, with a power-added efficiency (PAE) of 23 % while drawing 15.8 mA from a 1.8 V supply. The die area of the PA (pads included) is 2.1 mm2.

Inhaltsverzeichnis:Table of Contents:
1.Introduction1
1.1Motivation1
1.2Organization2
2.The Bluetooth standard3
2.1Bluetooth as branding-name3
2.2Bluetooth RF requirements4
2.3System design4
2.3.1Receiver architectures4
2.3.2Transmitter architectures6
3.RF CMOS technology9
3.1The foundry9
3.1.1Technology overview9
3.1.2Process Characteristic9
3.2Design Flow10
3.2.1Cadence10
3.2.2SpectreRF10
4.Integrated spiral inductors11
4.1View and physical dimension of spiral11
4.2Model for on-chip spiral inductors12
5.Low Noise Amplifier13
5.1Architecture choices13
5.1.1Recent studies13
5.1.2LNA Architectures13
5.1.3Architecture properties14
5.1.4Architecture choice14
5.2A little piece of theory15
5.2.1Standard MOS noise model15
5.2.2Noise Figure16
5.2.3Input impedance16
5.2.4Voltage Gain18
5.2.5Stability19
5.2.6Noise Figure20
5.3Design approach for the LNA21
5.3.1Circuit topology21
5.3.2RF circuit design strategy21
5.3.3DC operating point design strategy23
5.3.4Input matching24
5.3.5Voltage gain25
5.3.6Noise Figure26
5.3.7Stability27
5.3.8LNA core schematics with component values28
5.4Design approach for the attenuation path of the LNA29
5.4.1Circuit Topology29
5.4.2Switching network29
5.4.3Input matching31
5.4.4Attenuation32
5.4.5Switchable LNA schematics with […]

Leseprobe

Inhaltsverzeichnis

ID 4194

Krug, Florian: Design of 2.4 GHZ CMOS Frontend for Bluetooth / Florian Krug -

Hamburg: Diplomica GmbH, 2001

Zugl.: München, Technische Universität, Diplom, 2001

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Acknowledgments

First of all, I love Zurich. It is a wonderful place for working and living.

I would like to thank Federico Beffa and Dr. Urs Lott (acter AG) for their many suggestions

and constant support during this work. Fede and Urs show me the way of making

industrial RF circuits.

My thanks go to Professor Dr. Werner B¨

achtold from the Swiss Federal Institute of Tech-

nology Zurich, Electromagnetic Fields and Microwave Electronics Laboratory. Prof.

B¨

achtold is not only a brilliant scientist, but students are always welcome to him.

Professor Dr.

Peter Russer from the Technischen Universit¨

at M¨

unchen, Lehrstuhl f¨

Hochfrequenztechnik expressed his interest in my work and gave me the chance for

making my diploma thesis in Zurich.

Big thanks also go to Jean Wilwert, Edmund G¨

otz, Hans-Eberhard Kr¨

obel, Markus Scholz,

Dr. Bernd-Ulrich Klepser and Dr. Jakub J. Kucera from Wireless Products at Infineon

Technologies AG for there training on radio frequency circuit design and the nice time

in a genuine team.

Special thanks goes to the Siemens AG in Munich for their scholarship.

Mein Dank gilt Herrn Landeshauptmann Dr. Wendelin Weingartner f¨

ur seine großz¨

ugige

Spende.

Ein Dankesch¨

on geht ebenfalls an die Industriellenvereinigung Tirol f¨

ur die finanzielle Un-

terst¨

utzung dieser Arbeit.

Finally, I wish to thank the following persons: Christoph Balmer, Ray Ballisti, Renato Negra,

Andrea Orzati, Frank Ellinger, Guido Steiner, Olivier J.F. Martin and all members of

IFH.

TEX, UNIX and SUN: they gave me a lot of lucky moments in a surreal computing world.

Der gr¨

oßte Dank gilt meinen Eltern.

Zurich / Munich

Florian Krug March 2001

Abstract

The Bluetooth wireless technology is the worlds new short-range RF transmission standard

for small form factor, low-cost, short-range radio links between portable or desktop devices.

The technology promises to eliminate the confusion of cables, connectors and protocols con-

founding communications between today high tech products.

In the first step a 2.45 GHz Low Noise Amplifier (LNA), intended for use in a Bluetooth

receiver, has been designed in a standard 0.18 µm CMOS process. The amplifier provides

a simulated switchable forward voltage gain of +16 / -7.7 dB with a simulated noise figure

(NF) of only 3 dB while drawing 2.8 mA from a 1.8 V supply. The die area of the LNA (pads

included) is 0.79 mm

In the second step a 2.45 GHz Power Amplifier (PA), also intended for the Bluetooth

standard, has been designed in the same 0.18 µm CMOS process as for the LNA. The class-A

PA achieves a simulated forward gain (S

) of 23 dB and a simulated output 1 dB compression

point (P

1dB

) of 5.5 dBm, with a power-added efficiency (PAE) of 23 % while drawing 15.8

mA from a 1.8 V supply. The die area of the PA (pads included) is 2.1 mm

vii

Contents

Introduction

1.1

Motivation

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2

Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

The Bluetooth standard

2.1

Bluetooth as branding-name . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2

Bluetooth RF requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3

System design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.1

Receiver architectures . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.2

Transmitter architectures . . . . . . . . . . . . . . . . . . . . . . . . .

RF CMOS technology

3.1

The foundry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.1

Technology overview . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1.2

Process Characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2

Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.1

Cadence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.2

Spectre RF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Integrated spiral inductors

4.1

View and physical dimension of spiral inductor . . . . . . . . . . . . . . . . .

4.2

Model for on-chip spiral inductors

. . . . . . . . . . . . . . . . . . . . . . . .

Low Noise Amplifier

5.1

Architecture choices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1.1

Recent studies

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1.2

LNA Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1.3

Architecture properties

. . . . . . . . . . . . . . . . . . . . . . . . . .

5.1.4

Architecture choice . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2

A little piece of theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2.1

Standard MOS noise model . . . . . . . . . . . . . . . . . . . . . . . .

5.2.2

Noise figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2.3

Input impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2.4

Voltage Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2.5

Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2.6

Noise figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3

Design approach for the LNA core . . . . . . . . . . . . . . . . . . . . . . . .

CONTENTS

5.3.1

Circuit topology choice

. . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.2

RF circuit design strategy . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.3

DC operating point design strategy . . . . . . . . . . . . . . . . . . . .

5.3.4

Input matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.5

Voltage gain

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.6

Noise figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.7

Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3.8

LNA core schematics with component values . . . . . . . . . . . . . .

5.4

Design approach for the attenuation path of the LNA

. . . . . . . . . . . . .

5.4.1

Circuit Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4.2

Switching network . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4.3

Input matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4.4

Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4.5

Switchable LNA schematics with component values . . . . . . . . . . .

5.5

Summary of simulation results

. . . . . . . . . . . . . . . . . . . . . . . . . .

5.6

Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7

Measurement approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7.1

Simulation results

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7.2

Summary of simulation results . . . . . . . . . . . . . . . . . . . . . .

Power Amplifier

6.1

Architecture choices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1.1

Recent studies

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1.2

PA classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1.3

Architecture choice . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2

A little piece of theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.1

Efficiency definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.2

Class-A power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2.3

Loadline theory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3

Design approach for the PA . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3.1

Design approach for the output stage

. . . . . . . . . . . . . . . . . .

6.3.2

Design approach for the interstage matching

. . . . . . . . . . . . . .

6.3.3

Design approach for the input stage . . . . . . . . . . . . . . . . . . .

6.3.4

Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3.5

PA schematics with component values . . . . . . . . . . . . . . . . . .

6.4

Measurement approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4.1

Simulation results

. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4.2

Summary of simulation results . . . . . . . . . . . . . . . . . . . . . .

6.5

Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Bibliography

Abbreviation and symbols

Conceptual formulation

Curriculum vitae

Chapter 1

Introduction

The last few years have seen a remarkable amount of growth in the wireless communications

areas, and as a result, the demand for optimizing the circuits involved in wireless communica-

tion devices has increased dramatically. Not only has the demand for the circuits increased,

the amount of research done in this field has surged as well. Since in a portable wireless en-

vironment all circuits are drawing power from a small battery, it seems clear that one of the

most important aspects of the circuits that needs to be optimized, is the power consumption.

Additionally, since these devices are used in low cost products, the cost of the circuits must

be lowered as well.

1.1

Motivation

So it is time to tax ones brain about the motivation for this work.

Why people design products for the Bluetooth standard ?

The momentum behind Bluetooth has shown no signs of abating, despite recent market

delays. Annual shipments of Bluetooth-capable devices are projected to reach over 1.4 billion

nodes in 2005, up from just 56 million nodes in 2001. This will represent a sizeable silicon

(Si) market opportunity with semiconductor revenues of $5.3 billion by 2005 [35]. "Bluetooth:

More than a cable replacement" is a recently released study from Allied Business Intelligence.

It forecasts the penetration of Bluetooth into 17 different market segments, including mobile

handsets, notebooks, desktops and personal digital assistants (PDAs).

Why everybody needs a highly integrated RF transceiver ?

Afford ability and portability are the two principal requirements of wireless communica-

tions. For this approach the cost, battery life and form factor are the key parameters for a

mobile phone. To achieve this goal, a suited hardware technology is demanded. The right

answer to this problem are highly integrated circuits. In the paper [12] a lot of technical de-

tails about the recent advantages in RF integrated circuits are shown. A good review about

the design aspects of RF integrated circuits in different IC technologies (e.g. GaAs, CMOS)

is given in [30] or [31].

CHAPTER 1. INTRODUCTION

Why CMOS is one of the preferred IC technologies ?

The strongly emerging wireless communication market needs device technologies that are

capable to produce high product volumes at extremely low cost. Important is also a potentially

easier and faster System on Chip (SoC) integration. Those requirements are best met by

Complementary Metal Oxide Semiconductor (CMOS) technology. Consequently, substantial

research is in progress today to investigate and optimize CMOS for radio frequency (RF)

applications.

1.2

Organization

In this work different aspects of the development of Low Noise Amplifiers (LNA) and Power

Amplifiers (PA) for Bluetooth applications will be discussed.

Chapter 2

This chapter represents the Bluetooth standard. Especially, the requirements on the RF part

are highlighted. Also a review of the possible hardware architectures is given.

Chapter 3

It describes the used CMOS technology and the design flow.

Chapter 4

In this chapter the characteristics of the integrated spiral inductors are presented and a short

description of the used inductor model is given.

Chapter 5

This chapter describes the various topologies of LNAs and an LNA design scheme. Also the

realized LNA circuit and its layout are shown.

Chapter 6

In the last chapter the different PA choices are presented. A design procedure for linear power

amplifier is given. Moreover, the final layout of the PA is reported.

Chapter 2

The Bluetooth standard

Bluetooth is a short-distance wireless technology that spans telecommunications, personal

computing, networking, industrial, automotive and consumer electronic devices, allowing

voice and data connections up to 10 meters (100 meters with an additional power amplifier).

Bluetooth frees users from having to wrestle with numerous cords, gives the corporate and

consumer worlds access to easy synchronization and mobility during a cordless connection,

and opens up many possibilities for establishing quick, temporary connections.

2.1

Bluetooth as branding-name

Why was the wireless technology named "Bluetooth" ?

The heart of the Bluetooth brand identity is the name, which refers to the Danish king Harald

Bl°

atand (Bluetooth) who unified Denmark and Norway.

Is "Bluetooth" a trademark ?

The Bluetooth name is a trademark, and as such its spelling cannot be changed. It is always

to be used in English; it must not be translated into other languages. Fig. 2.1 shows the

official emblem of the Bluetooth technology.

Figure 2.1: Official Bluetooth emblem

Who may use the Bluetooth trademark ?

All Bluetooth Special Interest Group (SIG) members that have signed an adopters or pro-

moters agreement have a worldwide, royalty-free license to use the Bluetooth trademark in

accordance with the instructions provided in the Brand Book. Any Bluetooth member may

use the trademark in connection with products that comply with Bluetooth Specifications.

CHAPTER 2. THE BLUETOOTH STANDARD

A product must complete the Qualification Program to meet the requirements for complying

with the Bluetooth Specification. To get access to the figure mark and the combination mark,

a company has to sign the Bluetooth Trademark Agreement.

2.2

Bluetooth RF requirements

This section looks at the Bluetooth specification. The key information is taken from [9]

and [35].

The Bluetooth system is operating in the 2.4 GHz Industrial Scientific Medicine (ISM)

band. The following enumeration gives the most important specification items for the RF

part of a Bluetooth system:

· Carrier frequency: 2.4 to 2.4835 GHz

· The modulation scheme is Gaussian Frequency Shift Keying (GFSK), baseband filtered

with a 3 dB bandwidth of 500 kHz (is equal to a Bandwidth Time (BT) product of 0.5)

and a modulation index that can vary from 0.28 to 0.35 (nominal is the value 0.32).

· There are three transmit power classes with nominal outputs of 0, +4 and +20 dBm

and three mandatory steps of power control in the high-power class.

· To operate at higher power levels in the unlicensed bands, and to avoid interferences,

bluetooth transceivers use frequency hop spread spectrum (FHSS) with a nominal rate

of 1600 hops per second.

· The channel access method is time division multiple access (TDMA) with 625 µs frames

in half-duplex (TX and RX alternate in time) connections and a frequency hop between

each transmit and receive.

· The hop sequence is pseudo-random (length 2

) with the largest possible hop of 78

MHz.

· The Bluetooth system operates under Part 15 regulations in the US (47CFR15.247 [10])

as the lowest priority user and must not cause interference to licensed systems and must

accept all interference from other systems.

· Maximum data throughput: The asynchronous channel can support either an asymmet-

ric link with up to 721 kb/s in one direction and 57.6 kb/s in the other or a symmetric

link with 432.6 kb/s in both directions.

2.3

System design

2.3.1

Receiver architectures

Although there are many different radio architectures that can be used to implement a Blue-

tooth receiver four types are used in practise, for cost and performance reasons. Fig. 2.2

shows the likely used receiver architectures.

All of these rely on a single conversion with channel select filtering at only one frequency

which is enabled by the relaxed interference requirements (maximum interferer is only 40 dB

higher) in the Bluetooth specification.

2.3. SYSTEM DESIGN

BASEBAND

Demod

off chip

SAW

(a) High IF

Demod

BASEBAND

135

(b) Low IF

Demod

BASEBAND

AGC

135

correction

Demod

BASEBAND

AGC with DC offset

(d) Zero IF

Figure 2.2: Bluetooth receiver architectures

The Bluetooth specifications were developed with a High Intermediate Frequency (IF)

(Fig. 2.2(a)) and Low IF (Fig. 2.2(b)) architectures (the two architectures initially developed

by [36] and [37]). With regards to the costs, the very low IF architecture (Fig. 2.2(b)) is

CHAPTER 2. THE BLUETOOTH STANDARD

preferred.

High intermediate frequency

The architecture is shown in Fig. 2.2(a). A single conversion to an IF that is much greater

than the channel bandwidth. The most common IF is 110.6 MHz, due to the fact that low-cost

surface acoustic wave (SAW) filters developed for the Digital Enhanced Cordless Telephone

(DECT) phones fulfill also the Bluetooth channel-filter requirements (1.2 MHz bandwidth).

Since the relative bandwidth is so small (less than 1 %), the channel select filter requires high

quality factor (Q) elements, which are not available in current semiconductor processes and

so this filter must be off-chip.

Low intermediate frequency

The architecture shown in Fig. 2.2(b) performs a single signal conversion to an IF greater

than the channel bandwidth, usually in the 5-10 MHz range, to obtain a relative bandwidth

for the channel select filter of 10-20 percent. This allows much lower Q components which

can be realized on-chip. Although the Bluetooth specification has relaxed requirements for

the resulting in-band range, this architecture requires an image reject mixer.

Very low intermediate frequency

The architecture is shown in Fig. 2.2(c).

This receiver architecture works with a single

conversion to an IF that is one half of the channel bandwidth, in this case 500 kHz. The

filter needed in this approach is of low-pass type with a DC notch. This type of filter can be

monolithically integrated on most semiconductor processes. With the low modulation index

used by Bluetooth, the IF chain must be linear and so Automatic Gain Control (AGC) is

required to successfully demodulate the signal.

Zero intermediate frequency

The architecture which is referred to as direct conversion receiver is shown in Fig. 2.2(d).

The RF signal is mixed down directly to the baseband, requiring an I/Q down mixer and

separate baseband paths to maintain the negative frequency information. Channel selectivity

is accomplished with a low pass filter. While there is no image frequency for this architecture,

the local oscillator (LO) is in band, which creates a DC component that must be removed by

DC offset correction.

2.3.2

Transmitter architectures

While there is a variety of transmitter architectures that have been proposed, all published

implementations use a direct launch transmitter architecture. The channel bandwidth of

the transmitter signal is achieved by baseband filtering the data with an approximation of a

Gaussian filter with a 3 dB cutoff frequency of 500 kHz.

The three different techniques that can be applied to develop the modulation with the use

of a frequency synthesizer are shown in Fig. 2.3.

2.3. SYSTEM DESIGN

Synth

TX data

PLL Loop Filter

Gaussian data LPF

OUT

(a) Open-loop

TX data

Frac-N Synth

PLL Loop Filter

OUT

(b) Fractional-N modulation

Synth

TX data

Gaussian data LPF

Data Filter

OUT

PLL Loop Filter

Figure 2.3: Bluetooth transmitter architectures

Open loop modulation

The architecture is shown in Fig. 2.3(a). For this approach, the RF oscillator is first locked to

the transmit frequency by the Phase Locked Loop (PLL) and then the PLL loop is opened,

allowing the Voltage Controlled Oscillator (VCO) to run freely. At this point the modulation

waveform is applied to the VCO to deviate the frequency and generate the Frequency Shift

Keying (FSK) signal. Open-loop modulation is the simplest to implement but the VCO drift

must be controlled. In addition, the presence of strong interferers, including the harmonics of

other radios, can cause the transmitting VCO to lock to the wrong frequency. The Bluetooth

specification explicitly addresses this transmit architecture by allowing the center frequency

to drift during transmission of a data packet.

CHAPTER 2. THE BLUETOOTH STANDARD

Fractional-N modulation

The architecture is shown in Fig. 2.3(b). Since fractional-N synthesizers allow extremely

precise control of the VCO frequency, it is possible to modulate the VCO frequency by

programming the accumulators in a fractional-N synthesizer.

This has the advantage of

providing what is essentially a digital modulation of the transmit frequency and so does not

require any tuning. Being a closed-loop modulation technique, it is resistant to frequency

pulling by strong interferers. However, fractional-N synthesizers take up more die area and

are more difficult to implement than dual modulus or integer PLLs.

Dual port modulation

The architecture is shown in Fig. 2.3(c). Here the input signal is split: the low frequency

content is fed through the loop filter and the high frequency content is applied outside the

loop through a high-pass filter to the VCO. The amplitude of the high-frequency content

needs to be scaled, based on the VCO gain, to maintain the same net gain for the modulating

signal both inside and outside of the loop. The dual-port architecture allows the VCO to

remain locked by the PLL during the modulation, making it less sensible to frequency pulling

and frequency drift in a packet.

Chapter 3

RF CMOS technology

3.1

The foundry

The low noise and power amplifiers are designed in a 0.18 µm CMOS technology of Taiwan

Semiconductor Manufacturing Co. (TSMC). TSMC is the worlds largest dedicated semicon-

ductor foundry, providing the industry's leading process technology, library and IP options

and other leading-edge foundry services. TSMC operates two six-inch wafer fabs and six

eight-inch wafer fabs. The Company also has substantial capacity commitments at two joint

venture fabs (Vanguard and SSMC) and WaferTech. In the year 2000, TSMC produced the

foundry industry's first 300 mm customer wafers and began constructing three dedicated 300

mm fabs. Fabrication processes offered by TSMC include CMOS logic, mixed-mode / RF,

volatile and non-volatile memory, and BiCMOS. TSMC's corporate headquarters are in Hsin-

Chu, Taiwan. More information about TSMC is available through the World Wide Web at

www.tsmc.com [38].

3.1.1

Technology overview

TSMC 0.18-µm technology is a single poly, six metal layer process with low-k dielectrics.

The main feature of the process is the option of copper interconnects in the top two

metal layers. Upper metal layer traces, generally used to interconnect functional blocks, are

typically longer and have higher resistance than intra-block traces. Using copper, rather than

aluminum, reduces interconnect resistance and makes higher speeds possible.

An additional property of the process is the shallow trench isolation (STI). It improves

surface planarity, compared to older isolation techniques, making it possible to achieve high-

reliability metalization. STI also reduces capacitive coupling between adjacent transistors,

increasing circuit density and reducing power consumption.

The process has an NMOS transistor with a transit frequency f

of 62 GHz, while coupled

to a deep n-well option that provides a noise transmission reduction of 25 dB less than

traditional twin well processes. In addition a 3.3 V transistor can be added for I/O-port

circuits to get larger output signals.

3.1.2

Process Characteristic

The following table shows the important process characteristics for the 0.18-µm CMOS tech-

nology of TSMC.

CHAPTER 3. RF CMOS TECHNOLOGY

Feature

Physical property

Metal-layers

up to 6 layers

Contacted metal pitch

M1 0.46 µm, M2-5 0.56 µm, M6 0.90 µm

Core voltage

1.8 V

I/O voltage option

3.3 V

Physical gate

0.16 µm

Poly half-pitch

0.215 µm

Gate dielectric

dual

IOFF Spec. (worst case)

0.1 nA/µm

Lithography

Deep UV (phase shift mask)

Well formation

super steep (retrograde)

Isolation

STI (shallow trench isolation)

Salicide

CoSi

Capacitor

Mim

Inductor

Thick Metal(Top)

Intermetal dielectric

Low-K

Via fill

W or Cu plug

Ring oscillator delay

28 ps

6T SRAM Cell

4.65 µm

3.2

Design Flow

3.2.1

Cadence

The circuit design has been carried out with Design Framework II from Cadence Design

Systems, Inc. [39].

3.2.2

Spectre RF

The Spectre RF tools work like conventional low-frequency analog circuit simulators, e.g.

SPICE. The features of the tool set - envelope following analysis and time-domain noise

analysis - are claimed to make it easy to perform a number of important RF checks, such

as analyzing adjacent channel noise. The Spectre RF tool supports full-chip simulation of

transmitters, receivers, mixers, oscillators and PLLs used in 3G cell phones, Bluetooth and

other wireless applications. Incorporated in the RF IC design-flow, the tools will help the

designer to visualize the effects of digital and analog modulation schemes on RF carriers. It

will examine the effects of CMOS noise, and even the effects of packages and lead frames, on

an RF signal.

Details

Seiten
Erscheinungsform: Originalausgabe
Jahr: 2001
ISBN (eBook): 9783832441944
ISBN (Paperback): 9783838641942
DOI: 10.3239/9783832441944
Dateigröße: 793 KB
Sprache: Englisch
Institution / Hochschule: Technische Universität München – unbekannt
Erscheinungsdatum: 2001 (Juni)
Note: 1,0
Schlagworte: cmos bluetooth hochfrequenztechnik schaltungstechnik integrierte schaltung

Autor

Florian Krug (Autor:in)

Design of 2.4 GHZ CMOS Frontend for Bluetooth

Zusammenfassung

Leseprobe

Inhaltsverzeichnis

Details

Autor

Florian Krug (Autor:in)